The present invention relates to managing routings within a netlist, and more specifically to using buffers to manipulate signals within a netlist.
Hardware designs are typically hierarchical and modularity may be achieved by encapsulating logic functionality as a node in a design hierarchy. However, the functional hierarchy may not map to a two dimensional layout solution as the functional hierarchy typically does not consider of layout information, such as area and routing constraints. Further, due to strict enforcement of a single functional and physical hierarchy mapping, logic designs, and verification are less efficient. Further, design processes using hardware description language (HDL) are commonly constrained by physical constraints, and in many instances, automatically mapping functional hierarchy to physical hierarchy has failed to the difficulty in performing pin optimization, pin cloning, subway specifying, and connection routing. Thus, techniques that are able to utilize pin cloning and subway creation may make it possible to employ automatic mapping from a functional hierarchy into a physical hierarchy.